1. Field of the Invention
Example embodiments of the present invention relate to a semiconductor device and, more particularly, to a semiconductor device and a test system thereof in which a timing margin of signals within the semiconductor device may be detected by using a complementary clock signal of the semiconductor device.
2. Description of the Related Art
As semiconductor devices pursue higher integration and higher speed, a timing margin of signals within the semiconductor devices may become smaller. The timing margin of the signals is one of the many factors which affect whether the semiconductor device operates normally and operating speed of the semiconductor device. For example, the semiconductor device may operate abnormally when the timing margin of the signals is short, whereas the operating speed of the semiconductor device may be reduced even though the semiconductor device operates normally if the timing margin of the signals is large.
Based at least in part on the foregoing reason, internal circuits of a semiconductor device may be designed to optimize the timing margin of the signals. However, even though the internal circuits of the semiconductor device may be designed to optimize the timing margin of the signals within the semiconductor device, there may be a case where the timing margin of the signals within the semiconductor device is altered due to process dispersion that may occur during manufacturing of the semiconductor device and/or result from an operating circumstance of the semiconductor device.
However, a conventional semiconductor device and a test device thereof for testing the conventional semiconductor device does not provide a means for detecting the timing margin of the signals within the semiconductor device. The test system of a conventional semiconductor device merely provides the semiconductor device with electric signals according to a test program, and if the semiconductor device operates abnormally in response to the electric signals, the testing device determines the inappropriate timing margin of the signals within the semiconductor device may be one of the reasons for the abnormal operation.
FIG. 1 is a block diagram illustrating a conventional test system.
Referring to FIG. 1, the test system may include a test device 1 and a semiconductor device 2. The test device 1 may provide a semiconductor device 2 with electric signals, for example, clk, clkb, com, add, data, and Vref, in accordance with a test program and may analyze data tdata output from the semiconductor device 2 to determine whether the semiconductor device operates abnormally or not. The semiconductor device 2 may perform a prescribed operation in response to the electric signals clk, clkb, com, add, data, and Vref, which may be provided by the test device 1, and may output the data tdata to the test device 1.
A semiconductor device 2 may include a clock buffer 21 for buffering a clock signal clk and/or a complementary clock signal clkb to generate an internal clock signal, a column address generating circuit 22 for generating an column address CA from an address add in response to a read signal RE or a write signal WR, a column enable circuit 23 for generating a column enable signal CES in response to the read signal RE or the write signal WR and an internal clock signal pclk, a row address generating circuit 24 for generating a row address RA from the address add in response to an active signal ACTIVE, a row enable circuit 25 for generating a row enable signal RES in response to the active signal ACTIVE and the internal clock signal pclk, a column decoder 26 for generating a column selecting signal CSL in response to the column enable signal and the column address CA, a row decoder for generating a word line enable signal NEW in response to the row enable signal RES and the row address RA, a memory cell array 28 for reading or writing data from or to a memory cell in response to the column selecting signal CSL and the word line enable signal NEW, a sense amplifier 29 for detecting and amplifying data outputted from the memory cell array 28 and transmitting data to a data output circuit 211, a data input circuit 210 for inputting data to the memory cell array 28, a data output circuit 211 for outputting data tdata to an external system and/or test device 1, and a command decoder 212 for receiving and decoding a command signal corn to generate control signals RE, WR, ACTIVE, and MRS for controlling an operation of the semiconductor device 2.
The semiconductor device 2 may further include a test control circuit 213, which may be implemented by a mode register set and/or a fuse circuit. The test control circuit 213 may set the semiconductor device 2 to a test mode in response to a mode register set control code MRS provided from the command decoder 212.
As described above, the semiconductor device 2 may perform a prescribed operation in response to electric signals clk, clkb, corn, add, data, and Vref to output data tdata to a test device 1.
During a test mode, if the timing margin of the input signals of internal circuits 21 to 212 of the semiconductor device 2 is appropriate, the internal circuits 21 to 212 normally recognize the input signals and may generate data having information expected by the test device 1, whereas if the timing margin of the input signals of the internal circuits 21 to 212 of the semiconductor device 2 is inappropriate, the internal circuits 21 to 212 do not normally recognize the input signals and may not generate data having information expected by the test device 1.
For example, when a column enable signal CES is first generated and the column address CA is next generated so that the column enable signal CES and the column address CA have an appropriate timing margin, the column decoder 26 recognizes the column address CA and so performs a normal operation to generate the column selecting signals CSL. However, when the column enable signal CES and the column address CA have an inappropriate timing margin, the column decoder does not recognize the column address CA and cannot generate the column selecting signals CSL.
Otherwise, however, the column decoder does not recognize the column address CA, and so the column decoder cannot generate the column selecting signals.
The test device 1 may receive and may analyze the data tdata to confirm that the data tdata having the information expected by the test device 1 is received and thus, may determine that the semiconductor is operating normally and that the timing margin of the signals within the semiconductor device is appropriate. On the other hand, when the data tdata having the information expected by the test device 1 is not received, the test device 1 may determine that the semiconductor is operating abnormally and may determine the inappropriate timing margin of the signals within the semiconductor device may be one of reasons for the abnormal operation.
Accordingly, a conventional test system does not have a means for varying and detecting a timing margin of signals within a semiconductor device 2 and cannot determine a specific reason for the abnormal operation. Even if a conventional test system may determine that an abnormal operation is affected and/or caused by an inappropriate timing margin of signals within the semiconductor device, the test system may not determine which circuit is inaccurate in timing margin and how much of the timing margin inaccurate. In light of the above, time and cost to locate and/or debug a reason for an abnormal operation of a semiconductor device may be unnecessarily increased.
A conventional semiconductor device should secure enough timing margin of the signals to reduce the abnormal operation of the semiconductor device because the conventional semiconductor device cannot detect the optimum timing margin of the signals within the semiconductor device through the test system. In this case, however, even though the semiconductor device may operate normally, there may be a problem because the operating speed of the semiconductor device may be reduced.